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Roland W-30 Information
This is my little trove of technical information on the
Roland W-30 Music Workstation.
Contents
Processor
CPU
The central processor in the W-30 is an Intel N8097BH. It is a member of
the 8096 familay of 16-bit microcontrollers, with the addition of an
8-channel 10-bit ADC.
The following information was copied from a page at Auston Community College.
The 8096 is a 16-bit microcontroller with dedicated I/O subsystems and a
complete set of 16-bit arithmetic instructions including multiply and divide
operations. If it has the A/D function, it is called an 8097. The 8098/8938
is an 8-bit bus version of this part. The 8048 was optimized for general
control tasks while the 8051 was optimized for 8-bit math and single bit
boolean operations. The 8096 has been designed for high speed/high performance
control applications and its architecture is different from that of the 8048 or
8051. There are two major sections of the 8096: the CPU section and the I/O
section. Each of these sections can be subdivided into functional blocks.
The CPU of the 8096 uses a 16-bit ALU which operates on a 256-byte register
file instead of an accumulator. Any of the locations in the register file can
be used for sources or destinations for most of the instructions. This is
called a register to register architecture. Many of the instructions can also
use bytes or words from anywhere in the 64K byte address space as operands. In
the lower 24 bytes of the register file are the register-mapped I/O control
locations, also called Special Function Registers or SFRs. These registers are
used to control the on-chip I/O features. The remaining 232 bytes are general
purpose RAM, the upper 16 of which can be kept alive using a low current
power-down mode.
I/O FEATURES
Many of the I/O features on the 8096 are designed to operate with little CPU
intervention.
- The Watchdog Timer is an internal timer which can be used to reset the
system if the software fails to operate properly.
- The Pulse-Width-Modulation (PWM) output can be used as a rough D to A, a
motor driver, or for many other purposes.
- The A to D converter (ADC) has 8 multiplexed inputs and 10-bit resolution.
- The serial port has several modes and its own baud rate generator.
- The High Speed I/O section includes a 16-bit timer, a 16-bit counter, a
4-input programmable edge detector, 4 software timers, and a 6-output
programmable event generator.
OPERATIONS AND ADDRESSING MODES
The 8096 has 100 instructions, some of which operate on bits, some on bytes,
some on words and some on longs (double words). All of the standard logical and
arithmetic functions are available for both byte and word operations. Bit
operations and long operations are provided for some instructions. There are
also flag manipulation instructions as well as jump and call instructions. A
full set of conditional jumps has been included to speed up testing for various
conditions.
Bit operations are provided by the Jump Bit and Jump Not Bit instructions, as
well as by immediate masking of bytes. These bit operations can be performed on
any of the bytes in the register file or on any of the special function
registers. The fast bit manipulation of the SFRs can provide rapid I/O
operations. A symmetric set of byte and word operations make up the majority of
the 8096 instruction set. The assembly language for the 8096 (ASM-96) uses a
"B" suffix on a mnemonic to indicate a byte operation, without this suffix a
word operation is indicated. Many of these operations can have one, two or
three operands.
An example of a one operand instruction would be:
NOT Value1 ; Value1 : = 1's complement (Value1)
A two operand instruction would have the form:
ADD Value2,Value1 ; Value2 : = Value2 + Value1
A three operand instruction might look like:
MUL Value3,Value2,Value1 ; Value3 : = Value2 * Value1
The three operand instructions combined with the register to register
architecture almost eliminate the necessity of using temporary registers. This
results in a faster processing time than machines that have equivalent
instruction execution times, but use a standard architecture.
Long (32-bit) operations include shifts, normalize, and multiply and divide.
The word divide is a 32-bit by 16-bit operation with a 16-bit quotient and
16-bit remainder. The word multiply is a word by word multiply with a long
result. Both of these operations can be done in either the signed or unsigned
mode. The direct unsigned modes of these instructions take only 6.5
microseconds. A normalize instruction and sticky bit flag have been included in
the instruction set to provide hardware support for the software floating point
package (FPAL-96).
MAJOR I/O FUNCTIONS
- High Speed Input Unit Provides Automatic Recording of Events
- High Speed Output Unit Provides Automatic Triggering of Events and Real-Time
Interrupts
- Pulse Width Modulation Output to Drive Motors or Analog Circuits
- A to D Converter Provides Analog Input
- Watchdog Timer Resets 8096 if a Malfunction Occurs
- Serial Port Provides Synchronous or Asynchronous Link
- Standard I/O Lines Provide Interface to the External World when other
Special Features are not needed
INTERRUPTS
There are 20 different interrupt sources that can be used on the 8096.
The 20 sources vector through 8 locations or interrupt vectors. Control of
the interrupts is handled through the Interrupt Pending Register
(INT_PENDING), the Interrupt Mask Register (INT_MASK), and the I bit in the
PSW (PSW.9). The INT_PENDING register contains bits which get set by
hardware when an interrupt occurs. If the interrupt mask register bit for
that source is a 1 and PSW.9 = 1, a vector will be taken to the address
listed in the interrupt vector table for that source. When the vector is
taken the INT_PENDING bit is cleared. If more than one bit is set in the
INT_PENDING register with the corresponding bit set in the INT_MASK
register, the Interrupt with the highest priority will be executed.
Source |
Vector Location |
Priority |
(High Byte) |
(Low Byte) |
Software | 2011H | 2010H | Not Applicable |
Extint | 200FH | 200EH | 7 (Highest) |
Serial Port | 200DH | 200CH | 6 |
Software Timers | 200BH | 200AH | 5 |
HSI.0 | 2009H | 2008H | 4 |
High Speed Outputs | 2007H | 2006H | 3 |
HSI Data Available | 2005H | 2004H | 2 |
A/D Conversion Complete | 2003H | 2002H | 1 |
Timer Overflow | 2001H | 2000H | 0 (Lowest) |
The software can make the hardware interrupts work in almost any fashion
desired by having each routine run with its own setup in the INT_MASK
register. This will be clearly seen in the examples in section 4 which
change the priority of the vectors in software. The PSW, stores the INT_MASK
register in its lower byte so that the mask register can be pushed and
popped along with the machine status when moving in and out of routines. The
action of pushing flags clears the PSW which includes PSW.9, the interrupt
enable bit. Therefore, after a PUSHF instruction interrupts are disabled. In
most cases an interrupt service routine will have the basic structure shown
below.
INT VECTOR:
PUSHF
LDB INT_MASK, #xxxxxxxxB
EI
-
- ;Insert service routine here
-
POPF
RET
The PUSHF instruction saves the PSW including the old INT_MASK register. The
PSW, including the interrupt enable bit are left cleared. If some interrupts
need to be enabled while the service routine runs, the INT_MASK is loaded with
a new value and interrupts are globally enabled before the service routine
continues. At the end of the service routine a POPF instruction is executed to
restore the old PSW. The RET instruction is executed and the code returns to
the desired location. Although the POPF instruction can enable the interrupts
the next instruction will always execute. This prevents unnecessary building of
the stack by ensuring that the RET always executes before another interrupt
vector is taken.
PSW REGISTER |
BIT | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
FLAG | Z | N | V | VT | C | - | I | ST | INT_MASK |
Where:
- Z
- is the zero flag. It is set when the result of an operation is zero.
- N
- is the negative flag. It is set to the algebraically correct sign of the
result regardless of overflows.
- V
- is the overflow flag. It is set if an overflow occurs.
- VT
- is the overflow trap flag. It is set when the VT flag is set and cleared by
JVT, JNVT, or CLRVT.
- C
- is the carry flag. It is set if a carry was generated by the prior
operation.
- I
- is the global interrupt enable bit.
- ST
- is the sticky bit. It is set during a right shift if a one was shifted into
and then out of the carry flag.
- INT_MASK
- is the interrupt mask register and contains bits which individually
enable the 8 interrupt vectors.
On-Chip I/O
All of the on-chip I/O features of the 8096 can be accessed through the special
function registers. The advantage of using register-mapped I/O is that these
registers can be used as the sources or destinations of CPU operations. There
are seven major I/O functions. Each one of these will be considered with a
section of code to exemplify its usage. The first section covered will be the
High Speed I/O, (HSIO), subsystem. This section includes the High Speed Input
(HSI) unit, High Speed Output (HSO) unit, and the Timer/Counter section.
TIMER/COUNTERS
The 8096 has two time bases, Timer 1 and Timer 2. Timer 1 is a 16-bit free
running timer which is incremented every 8 state times. (A state time is 3
oscillator periods, or 0.25 microseconds with a 12 MHz crystal.)
A to D CONVERTER
The 8097 has a 10-bit A to D converter that can use any one of eight input
channels. The conversions are done using the successive approximation method,
and require 168 state times (42 microseconds with a 12 MHz clock). Since most
of the analog inputs which are monitored by a microcontroller change very
slowly relative to the 42 microsecond conversion time, it is acceptable to use
a capacitive filter on each input instead of a sample and hold. The 8097 does
not have an internal sample and hold, so it is necessary to ensure that the
input signal does not change during the conversion time. The input to the A/D
must be between ANGND and VREF. ANGND must be within a few millivolts of VSS
and VREF must be within a few tenths of a volt of VCC.
Using the A to D converter on the 8097 can be a very low software
overhead task because of the interrupt and HSO unit structure. The A to D
can be started by the HSO unit at a preset time. When the conversion is
complete it is possible to generate an interrupt. By using these features
the A to D can be run under complete interrupt control. The A to D can also
be directly controlled by software flags which are located in the
AD_RESULT/AD_COMMAND Register.
PWM REGISTER
Analog output is provided by a Pulse Width Modulated (PWM) signal. It is a
variable duty cycle, fixed frequency waveform that can be integrated to provide
an approximation to an analog output. The frequency is fixed at a period of 64
microseconds for a 12 MHz clock speed. Controlling the PWM simply requires
writing the desired duty cycle value (an 8-bit value) to the PWM Register.
INTERNAL CONTROL REGISTERS
The 8096 has 256 bytes of internal RAM, some of which have special functions
related to the I/O features.
Address | Register | Note |
Read | Write |
F0H - FFH | Power-Down RAM | Contents preserved by voltage on VPD pin during power-down mode. |
1AH - EFH | Internal Register File (RAM) | May be byte- , word- or long word-addressed. |
19H | Stack Pointer | If no stack needed, can be used as ordinary registers. |
18H |
17H | | PWM_Control | |
16H | IOS1 | IOC1 | |
15H | IOS0 | IOC0 | |
14H | Reserved | |
13H | |
12H | |
11H | SP_Stat | SP_Con | Used to query amnd control the serial port. |
10H | IO Port 2 | IO Port 2 | |
0FH | IO Port 1 | IO Port 1 | |
0EH | IO Port 0 | Baud_Rate | |
0DH | Timer2 (Hi) | Reserved | |
0CH | Timer2 (Lo) | |
0BH | Timer1 (Hi) | |
0AH | Timer1 (Lo) | Watchdog | |
09H | INT_Pending | INT_Pending | |
08H | INT_Mask | INT_Mask | |
07H | SBUF (Rx) | SBUF (Tx) | These are double-buffered: a byte can be sent/received even while one is being processed by the UART. |
06H | HSI_Status | HSO_Command | |
05H | HSI_Time (Hi) | HSO_Time (Hi) | |
04H | HSI_Time (Lo) | HSO_Time (Lo) | |
03H | AD_Result (Hi) | HSI_Mode | |
02H | AD_Result (Lo) | AD_Command | |
01H | R0 (Hi) | R0 (Hi) | Constant 0, used for addressing |
00H | R0 (Lo) | R0 (Lo) |
Note:
Do not read or write registers marked as Reserved else bad vibes
might be felt, the heavens shall open and swallow you whole, and you will
receive bad karma for the rest of eternity. You have been warned!!!
Instruction Set
ADDRESSING MODES
One operand of most of the instructions can be used with any one of six
addressing modes. These modes increase the flexibility and overall execution
speed of the 8096. The addressing modes are: register-direct, immediate,
indirect, indirect with auto-increment, and long and short indexed.
The fastest instruction execution is gained by using either register direct or
immediate addressing. Register-direct addressing is similar to normal direct
addressing, except that only addresses in the register file or SFRs can be
addressed. The indexed mode is used to directly address the remainder of the
64K address space. Immediate addressing operates as would be expected, using
the data following the opcode as the operand.
Both of the indirect addressing modes use the value in a word register as the
address of the operand. If the indirect auto-increment mode is used then the
word register is incremented by one after a byte access or by two after a word
access. This mode is particularly useful for accessing lookup tables.
Access to any of the locations in the 64K address space can be obtained by
using the long indexed addressing mode. In this mode a 16-bit 2's complement
value is added to the contents of a word register to form the address of the
operand. By using the zero register as the index, ASM96 (the assembler) can
accept "direct" addressing to any location. The zero register is located at
0000H and always has a value of zero. A short indexed mode is also available to
save some time and code. This mode uses an 8-bit 2's complement number as the
offset instead of a 16-bit number.
ASSEMBLY LANGUAGE
The multiple addressing modes of the 8096 make it easy to program in assembly
language and provide an excellent interface to high level languages. The
instructions accepted by the assembler consist of mnemonics followed by either
addresses or data. The addresses or data are given in different formats
depending on the addressing mode. These modes and formats are shown below.
Additional information on 8096 assembly language is available in the MCS-96
Macro Assembler Users Guide.
INSTRUCTION FORMAT
Mode | Format | Description |
Direct | Mnem Dest or Src1 | One operand direct |
Mnem Dest, Src1 | Two operand direct |
Mnem Dest, Src1, Src2 | Three operand direct |
Immediate | Mnem # Src1 | One operand immediate |
Mnem Dest, #Src1 | Two operand immediate |
Mnem Dest, Src1, #Src2 | Three operand immediate |
Indirect | Mnem [addr] | One operand indirect |
Mnem [addr]+ | One operand indirect auto-increment |
Mnem Dest, [addr] | Two operand indirect |
Mnem Dest, [addr]+ | Two operand indirect auto-increment |
Mnem Dest, Src1, [addr] | Three operand indirect |
Mnem Dest, Src1, [addr]+ | Three operand indirect auto-increment |
Indexed | Mnem Dest, offs [addr] | Two operand indexed (short or long) |
Mnem Dest, Src1, offs [addr] | Three operand indexed (short or long) |
Where:
- Mnem
- is the instruction mnemonic
- Dest
- is the destination register
- Src1,Src2
- are the source registers
- addr
- is a register containing a value to be used in computing the address of an operand
- offs
- is an offset used in computing the address of an operand
8096 INSTRUCTION SUMMARY
Download the 8096 Instruction Set Summary:
PDF or
TeX.
8096 INSTRUCTION CODES
Download the 8096 Instruction Opcodes:
PDF or
TeX.
Physical Details
PACKAGING
Type | Package | Without A/D | With A/D |
ROMless | 48-pin | | 8095BH or CH |
68 pin | 8096BH | 8097BH |
ROM | 48 pin | | 8395BH |
68 pin | 8396BH | 8397BH |
EPROM | 48 pin | | 8795BH |
68 pin | 8796BH | 8797BH |
The 48-pin version is offered in DIP, while the 68-pin is available in a PLCC,
a PGA, or a type "B" Leadless Chip Carrier.
PINOUTS
PGA/LCC | PLCC | DIP48 | Name |
| PGA/LCC | PLCC | DIP48 | Name |
1 | 9 | 41 | ACH7/P0.7/PMOD.3 | | 35 | 43 | 16 | READY |
2 | 8 | 40 | ACH6/P0.6/PMOD.2 | | 36 | 42 | - | T2RST/P2.4 |
3 | 7 | - | ACH2/P0.2 | | 37 | 41 | - | BHE\/WRH\ |
4 | 6 | - | ACH0/P0.0 | | 38 | 40 | 14 | WR\/WRL\ |
5 | 5 | - | ACH1/P0.1 | | 39 | 39 | 13 | PWM/P2.5/PDO\/SPROG\ |
6 | 4 | - | ACH3/P0.3 | | 40 | 38 | - | P2.7 |
7 | 3 | - | NMI | | 41 | 37 | 12 | VPP |
8 | 2 | 39 | EA\ | | 42 | 36 | 11 | VSS |
9 | 1 | 38 | VCC | | 43 | 35 | 10 | HSO.3 |
10 | 68 | 37 | VSS | | 44 | 34 | 9 | HSO.2 |
11 | 67 | 36 | XTAL1 | | 45 | 33 | - | P2.6 |
12 | 66 | 35 | XTAL2 | | 46 | 32 | - | P1.7 |
13 | 65 | - | CLKOUT | | 47 | 31 | - | P1.6 |
14 | 64 | - | BUSWIDTH | | 48 | 30 | - | P1.5 |
15 | 63 | - | INST | | 49 | 29 | 8 | HSO.1 |
16 | 62 | 34 | ALE/ADV\ | | 50 | 28 | 7 | HSO.0 |
17 | 61 | 33 | RD\ | | 51 | 27 | 6 | HSO.5/HSI.3 |
18 | 60 | 32 | AD0/P3.0 | | 52 | 26 | 5 | HSO.4/HSI.2 |
19 | 59 | 31 | AD1/P3.1 | | 53 | 25 | 4 | HSI.1 |
20 | 58 | 30 | AD2/P3.2 | | 54 | 24 | 3 | HSI.0 |
21 | 57 | 29 | AD3/P3.3 | | 55 | 23 | - | P1.4 |
22 | 56 | 28 | AD4/P3.4 | | 56 | 22 | - | P1.3 |
23 | 55 | 27 | AD5/P3.5 | | 57 | 21 | - | P1.2 |
24 | 54 | 26 | AD6/P3.6 | | 58 | 20 | - | P1.1 |
25 | 53 | 25 | AD7/P3.7 | | 59 | 19 | - | P1.0 |
26 | 52 | 24 | AD8/P4.0 | | 60 | 18 | 2 | TXD/P2.0/PVER/SALE |
27 | 51 | 23 | AD9/P4.1 | | 61 | 17 | 1 | RXD/P2.1/PALE |
28 | 50 | 22 | AD10/P4.2 | | 62 | 16 | 48 | RESET\ |
29 | 49 | 21 | AD11/P4.3 | | 63 | 15 | 47 | EXTINT/P2.2/PROG |
30 | 48 | 20 | AD12/P4.4 | | 64 | 14 | 46 | VPD |
31 | 47 | 19 | AD13/P4.5 | | 65 | 13 | 45 | VREF |
32 | 46 | 18 | AD14/P4.6 | | 66 | 12 | 44 | ANGND |
33 | 45 | 17 | AD15/P4.7 | | 67 | 11 | 43 | ACH4/P0.4/PMOD.0 |
34 | 44 | - | T2CLK/P2.3 | | 68 | 10 | 42 | ACH5/P0.5/PMOD.1 |
Note:
- DIP48 pin 15 is N/C
- xxx\ indicates inverse logic (active low)
PIN DESCRIPTIONS
Symbol | Name & Function |
VCC | Main supply voltage (5V) |
VSS | Digital circuit ground (0V). There
are two VSS pins both must be connected. |
VPD | RAM standby voltage (5V). This
voltage must be present during normal operation. In a Power Down condition
(i.e. VCC drops to zero), if RESET\ is activated before VCC drops below spec
and VPD continues to be held within spec, the top 16 bytes in the Register
File will retain their contents. RESET\ must be held low during the Power
Down and should not be brought high until VCC is is within spec and the
oscillator has stabilized. |
VREF | Reference voltage for the A/D
converter (5V). VREF is also the supply voltage to the analog portion of the
A/D converter and the logic used to read Port 0. |
ANGND | Reference ground for the A/D
converter. Must be held at nominally the same potential as VSS. |
VPP | Programming voltage for the EPROM
parts. It should be +12.75 V for programming. This pin must be left floating
in the application circuit. |
XTAL1 | Input of the oscillator inverter
and of the internal clock generator. |
XTAL2 | Output of the oscillator
inverter. |
CLKOUT | Output of the internal clock
generator. The frequency of CLKOUT is 1/3 the oscillator frequency. It has
33% duty cycle. |
RESET\ | Reset input to the chip. Input
low for at least 2 state times to reset the chip. The subsequent low-to-high
transition re-synchronizes CLKOUT and commences a 10-state-time sequence in
which the PSW is cleared, a byte read from 2018H loads CCR, and a jump to
location 2080H is executed. Input high for normal operation. RESET\ has an
internal pullup. |
BUSWIDTH | Input for bus width
selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If it is a
zero an 8-bit cycle occurs. If CCR bit 1 is 0, the bus is always an 8-bit
bus. If this pin is left unconnected, it will rise to VCC. |
NMI | A positive transition causes a
vector to external memory location 0000H. External memory from 00H through
0FFH is reserved for Intel development systems. |
INST | Output high during an external
memory read indicates the read is an instruction fetch. INST is valid
throughout the bus cycle. |
EA\ | Input for memory select (External
Access). EA\ equal to a TTL-high causes memory accesses to locations 2000H
through 3FFFH to be directed to on-chip ROM/EPROM. EA\ = +12.5 V causes
execution to begin in the Programming Mode. EA\ has an internal pulldown,
so it goes to 0 unless driven otherwise. |
ALE/ADV\ | Address Latch Enable or
Address Valid output, as selected by CCR. Both pin options provide a latch
to demultiplex the address from the address/data bus. When the pin is ADV\,
it goes inactive high at the end of the bus cycle. ADV\ can be used as a
chip select for external memory. ALE/ADV\ is activated only during external
memory accesses. |
RD\ | Read signal output to external
memory. RD\ is activated only during external memory reads. |
WR\/WRL\ | Write and Write Low output to
external memory, as selected by the CCR. WR\ will go low for every external
write, while WRL\ will go low only for external writes where an even byte is
being written. It is activated only during external memory
writes. |
BHE\/WRH\ | Bus High Enable or Write
High output to external memory, as selected by the CCR. BHE\=0 selects the
bank of memory that is connected to the high byte of the data bus. A0=0
selects the bank of memory that is connected to the low byte of the data
bus. Thus accesses to a 16-bit wide memory can be to the low byte only
(A0=0, BHE\=1), to the high byte only (A0=1, BHE\=0), or both bytes (A0=0,
BHE\=0). If the WRH\ function is selected, the pin will go low if the bus
cycle is writing to an odd memory location. |
READY | Ready input to lengthen external
memory cycles, for interfacing to slow or dynamic memory, or for bus
sharing. If the pin is high, CPU operation continues in a normal manner. If
the pin is low prior to the falling edge of CLKOUT, the memory controller
goes into a wait mode until the next positive transition in CLKOUT occurs
with READY high. The bus cycle can be lengthened by up to 1 microS. When the
external memory is not being used, READY has no effect. Internal control of
the number of wait states inserted into a bus cycle held not ready is
available through configuration of CCR. READY has a weak internal pullup, so
it goes to 1 unless externally pulled low. |
HSI | Inputs to High Speed Input. Four
HSI pins are available: HSI.0, HSI.1, 2 & 3. Two of them (HSI.2 & 3)
are shared with the HSO Unit. The HSI pins are also used as inputs by EPROM
parts in Programming Mode. |
HSO | Outputs from High Speed OUtput
Unit. Six HSO pins are available: HSO.1 ....5. Two of them (HSO.4 & 5)
are shared with the HSI Unit. |
Port 0 | 8-bit high impedance input-only
port. These pins can be used as digital inputs and/or as analog inputs to
the on-chip A/D converter. These pins are also a mode input to EPROM parts
in the Programming Mode. |
Port 1 | 8-bit quasi-bidirectional I/O
port. |
Ports 3 & 4 | 8-bit bi-directional
I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups. Ports 3
& 4 are also used as a command, address and data path by EPROM parts
operating in the Programming Mode. |
Further Reading
For more detailed information, check the Intel web page:
http://developer.intel.com/design/mcs96/docs_mcs96.htm
Much of the information in this document came from Intel data books and from
the file Using the 8096.
*sigh*
This document and the 8x9x Users Manual have been removed from the Intel website.
I am therefore making them available from this site:
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