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Roland W-30 Information

This is my little trove of technical information on the Roland W-30 Music Workstation.

Contents


System Architecture


My ultimate dream is to completely rewrite the W-30's operating software. As part of that I am investigating the W-30's internal system architecture, the results of which are rpesented here.

ROM MONITOR

To start with, read Peter Heitzer's page on S-50 hacking. He has found a simple ROM monitor within the S-50 boot ROMs, which talks to a terminal connected to the MIDI ports (in/out). To help him, he has also written an 8096 disassembler, which you can download and compile (it compiles fine under GCC, but it might ask you to change gets() to something else, like fgets()).

Now for the fun stuff. With the above boot ROM images I have started closely examining the W-30, and after a few minutes hunting it appears the W-30 also has a simple ROM monitor inside it! To quote the machine itself:

i8096 MT MONITER Ver 4.0 [ ON LINE ]

This has been copied straight out of the boot ROM data.

Further investigation of the boot ROM's indicates that this monitor mode is entered on the W-30 by holding down USER and turning it on. Communication is through the MIDI port to a terminal running at 31,250 baud (would have been better to use, say, 9600 baud. Oh well). The commands available are:

CommandArgsDescription
/   Prints a slash and returns to the main loop
R addr count Read count bytes starting at addr
W addr count b1 b2 ... Write count bytes b1 b2 ... to memory starting at addr
G addr arg Jump to code at addr with word arg in word register R1C
I addr count val Fill memory with val starting at addr for count bytes
M   Prints monitor version string
S {L|H}{B|0..7} Selects upper or lower memory page:
  • SL0..SL7 -- select lower memory page 0..7
  • SHB -- select upper memory base page (page 1)
  • SH0 -- select upper memory page 2
  • SH1 -- select upper memory page 3
I don't know why they didn't choose SH1..3 for the upper memory pages. Oh well, that's the way it works folks!

MEMORY ARCHITECTURE

The W-30 has a very interesting memory architecture, with the limited 64k address space of the 8097 split into several distinct segments, some of which have odd behaviour. But, I must confess, it is amazing how the Roland engineers squeezed it all into a meagre 64k!

Before presenting the memory map in detail, first an explanation. The 8097 processor is von Neumann machine, with code and data sharing the same address space. Well, in this case not quite. If you decode some control pins you can work out if the processor is accessing code or data.

The bottom 16k of space (0000h - 3FFFh) is split into two parts: code space and data space. The code part is where the boot ROMs sit, filling the entire 16k block. However, on top of this, in data space, we have seven banks of (almost) 8k of RAM. Why almost? Because the bottom 256 bytes will always refer to the processor's internal registers. And why seven? Because block 0 is where the boot ROM appears for accessing its own constant data tables. Note that this 56k of memory is data only -- if you try loading code into it and jumping to your code, instead you'll end up somewhere in boot ROM code.

The next major memory segment is from 4000h to 8000h. This is a single 16k block of RAM that is available for both code and data. The initial loader program from disk is loaded into 4000h-6000h, with execution starting at 4004h (the OS system entry point). Also, all the interrupt vector addresses point to the bottom of this page:

InterruptVector Address (hex)
OS Start Entry 4004
Timer Overflow 4008
AD Conversion 400C
HSI Data Available 4010
HSO 4014
HSI.0 4018
Software Timers 401C
Serial Port 4020
External Int 4024
Software Trap 4028

The third block is from 8000h-C000h and consists of three pages of 16k RAM that can be used for code and/or data. This brings the total amount of available data/code RAM to (7 * 8k + 16K + 3 * 16k) 120k (actually slightly under, by about 1,700 bytes). Which is not bad when you consider that there is 128k of RAM on the board: 94% of the board RAM is available to the programmer.

The next chunk of memory, from C000h-FFFFh is where the really fun stuff is -- all the hardware registers, for such things as the LCD, the floppy disk, the synthesizer engine, the SCSI controller, and the wave RAM.

Wave Storage

Which brings us to one of the most interesting parts of the memory system (and the heart of this workstation): the wave memory. It is split into 128 blocks of 4,096 samples (512k samples total) which is accessed in a most bizarre way, depending on whether you're reading from it or writing to it, and whether you want random or sequential access.

Random Access

The simplest mode is random access. The method is similar for both read and write access:

  • Write block number to C011h
  • Set the sample address by reading or writing to (addr * 2) + E001h
  • Access sample through C009h (low byte) and C00Bh (high byte)

The sample data is 12-bits left-shifted, with the bottom bits set to 0. So the 16-bit value read looks like:

Access RegisterC00BC009
Nibble3210
Sample Data12-bit Sample0000

I think the samples are stored as signed 2's-complement values, with the top bit being the sign bit.

Sequential Access

This mode is best suited to block reads and writes, saving the cost of setting the next sample address every time. It is mainly used for transferring sample data to/from the floppy and SCSI disks.

Operation is similar to random access except for specifying the sample address. Every block access must start at the beginning of a sample block. The address counter is reset by reading or writing to/from address FFFFh, and the sample data is accessed through C809H and C80Bh:

Reading:

  • Read from (addr * 2) + E001h
  • Write block number to C011h
  • Read from C809h (low byte) and C80Bh (high byte)

Writing:

  • Write (anything) to FFFFh
  • Write block number to C011h
  • Write to C809h (low byte) and C80Bh (high byte)

Once the address counter has been reset and the block number has been loaded you can read or write an entire 4,096 sample block by repeated accesses to C809h/C80Bh.

My guess is that within the memory controller of the sample chip is an address counter that can be set at some value (by writing to E001h + 2 * addr), reset (by writing to FFFFh), and auto-incremented if bit 11 of the register address is set (i.e. reading from C009h does not auto-increment, but reading from C809h does). There may even be separate address counters for read and write access, but as yet I don't have enough information to say either way. Let's just say it's a possibility, which may have some uses (especially for filters, etc)

MEMORY MAP

Here is the internal memory map of the W-30, as ascertained while examining the boot ROM code. As I do not have the original source code this is based very much on code examination and guessing.

0000Registers (256 bytes)
0100
(7.75k)
(SL0)
Boot
ROM
SL1SL2SL3SL4SL5SL6SL7
2000
(8k)
 
4000
(8k)
OS Code (RAM)
6000
(8k)
System RAM
8000
(16k)
SHBSH0 SH1
C000
(16k)
I/O and Wave RAM
FFFF

Obviously, this is very much work-in-progress. One day I would like a complete memory map. I think that is someway off yet.

MAIN BOARD FEATURES

Here is a list of the ICs on the main board.

Manufacturer Type ID Notes (some are guesses...)
RolandR15229884 TVF16 IC32TVF
RolandRD65006GF376 IC31TVF Interface Gate Array
RolandR15529883
MB654419U
IC33Wave ROM & Assign Gate Array
RolandR15229874
SA-16
IC28Wave Gate Array
RolandR15179934-00
LH534145
IC29Wave ROMs
RolandR15179934-00
LH534146
IC30
RolandR15239107
M60013-0137FP
IC7I/O Gate Array
RolandRDD63H149 IC6Keyboard Scanner Gate Array
FujitsuMB89352AP IC16SCSI Protocol Controller
Hewlett-Packard6N137 IC27MIDI In opto-isolator
MitsubishiM5M44256AP-10 IC21-26256k x 4 Fast Pagemode DRAM
Sample memory, 768kb total (512k samples)
FujitsuMBM27C64-20 IC19,20The boot ROMs
TISN74HC573N IC17,18Octal Latch
Address Latches
IntelN8097BH IC11Central Processor
HitachiHM65256BLSP-12 IC12-15,19,2032k x 8 PSRAM
System RAM, 128kb in total
WDCWD1772-PH 02-02 IC1Floppy Disk Controller
Note the "02-02" -- see notes on FDC hacks below...
SanyoLC3517AS-12 IC42k x 8 SRAM

DISPLAY BOARD FEATURES

This list documents the chips on the LCD front panel.

Manufacturer Type ID Notes (some are guesses...)
ToshibaT7900???Column driver
ToshibaTC5565AFL-15L???SRAM for LCD panel
ToshibaT6963C???LCD controller

Thanks to Dave Fenwick for supplying the information about the LCD chips.

I will be filling in details as and when I found out about these.

FEATURES I'D LIKE IN THE W-30

This is my list of features I'd like to see in the W-30 OS. Over time it may well expand, and I'd also be happy to add other people's suggestions.

  • Support large-capacity HD 1.44Mb disks
  • PC disk format support
  • WAV/AIFF read/write
  • Support MIDI Sample Dump Standard (SDS)
  • Realtime control of filter cutoff frequency
  • Expand beyond 80Mb disk volume limit
  • Support for newer CDROM drives
  • Boot from ZIP disk
  • Fit ZIP drive in place of floppy drive (thanks to Lars Esser)

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